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SiFive’s newly announced Performance P650 RISC-V processor core is intended for high-end servers and other applications requiring large bays of multiple processor cores.
The core of the P650 processor is a 64-bit implementation of the RISC-V architecture with a failed pipeline and advanced branch prediction. The new RISC-V core arrives months after SiFive introduced its Performance P550 processor core.
The P650 brings a pair of attributes that put it in the realm of high-end server processors. First, SiFive made some performance improvements specific to the processor architecture, including a 4-width instruction split (increased from the 3-width split of the P550 core) to three threads. . The Performance P650 core has a 13-step load / store pipeline and a separate 10-step integer execution pipeline.
SiFive was silent on floating point capabilities for the kernel in its public statement, although the block diagram above shows a floating point unit (FPU). During a presentation describing the Performance P550 core at the Linley Processor Forum in October, SiFive showed two slides that previewed a next-generation processor core. One slide revealed that the next-gen processor core will feature a double-precision 64-bit FPU and bit manipulation extensions.
To support its intended use as a server processor, the P650 kernel supports virtual software environments by implementing the RISC-V “H” hypervisor instruction extensions. In addition, the new kernel is designed to be implemented in more advanced process technology than the P550 kernel. SiFive claims that the focused process node combined with architectural and other design enhancements gives the P650 core a 50% performance boost over the P550 core.
More than a processor core
Among the second set of attributes required by high performance servers, the features that SiFive has built into its P650 processor core, is the ability to implement scalable and consistent multi-core processor clusters with four to 16 processor cores per cluster. Each P650 processor core has separate L1 instruction and data caches of up to 128KB, as well as a certain amount of L2 cache, which is divided into two banks.
SiFive did not disclose the maximum L2 cache size for the Performance P 650 kernel, but the L2 cache on the earlier P550 kernel can be up to 256KB. This is not much larger than the L1 caches of the P650 kernel, this which lets expect the maximum L2 cache size to be a bit larger for the new kernel.
In fact, SiFive’s next-gen kernel preview slide revealed that the L2 cache can be up to 2MB. P650 processor core clusters can also share an L3 cache of up to 1MB per core. Presumably, that means a shared L3 cache of up to 16MB, with 16 processor cores.
The earlier design of the P550 core creates multicore clusters through shared multiport access to the L3 cache. Four P550 Performance cores share an L3 cache. The Performance P650 core will use an as yet undisclosed consistent interconnect to implement clustering, although the details of SiFive’s announcement mention “clean and consistent NoC interfaces”.
The SiFive preview showed a similar multiport cache configuration for a P650 quad-core cluster, and a second next-gen preview shows four 4-core clusters connected by a network on a chip.
In addition to the mechanics of coherent clustering, SiFive has designed additional system hardware features for P650 multicore processor clusters, such as platform-level memory management and interrupt control units, required for the implementation of full server processor clusters. The details published by SiFive also mention “advanced security and encryption features”, without further details.
SiFive said it will offer some customers a preview of the P650 architecture in early 2022, with general availability by mid-year. While SiFive didn’t mention any of these major customers, Intel announced in June that it would be implementing SiFive’s P550 Performance core for its Horse Creek platform. The Horse Creek platform would be implemented on Intel’s 7nm processing technology, renamed “Intel 4”.
The ecosystem question remains unanswered: hardware alone does not win over server processor sockets. This has been a hard lesson for many companies aspiring to place Arm processor cores in servers. There is already a growing list of failed projects that have attempted to break into servers with Arm cores.
Chip vendors that have tried and failed include AMD, Broadcom, Calxeda, Cavium, Huawei, Nvidia, Qualcomm, Samsung, and Tianjin Phytium.
Although Arm cores are making inroads into servers – AWS Graviton, Fujitsu A64FX, and Marvell ThunderX and ThunderX2 processors among them – the process has been slow. Server processors based on the RISC-V architecture, including the SiFive P650 core, will encounter similar ecosystem-related resistance from server vendors and data center architects as SiFive and others are trying to move the x86 processor architecture from its throne.
Nonetheless, SiFive fanatics are convinced that their preferred architecture will eventually succeed.
SiFive will provide more details on its Performance P650 processor core and future RISC-V-based cores during a presentation at next week’s RISC-V Summit 2021 in San Francisco.